Digital variable frequency oscillators (hereinafter referred to as “VFO”) have been used to play back, e.g., data of magnetic recording disk. In general, VFO is built with an analogue circuit. However, the analogue circuit is hard to design since the tuning of resistance value and capacitance value with each other is required. Also, it is difficult to reduce the area of chip in the analogue circuit.
Therefore, recently, the digitalization of VFO has been desired. In reply to the desire, for example, a digital VFO using a counter has been suggested in Japanese patent application laid-open No.03-227123 (1991).
FIG. 1 is a block diagram showing the conventional VFO disclosed in Japanese patent application laid-open No. 03-227123. In the conventional VFO, there is provided a normalization circuit 32 to generate reference data with one clock width in reference clock from playback data 31 by a reference clock. Here, playback data 31 is the signal to be output from, e.g. a floppy disk drive device. Also, there is provided a counter 33 that is a binary counter with a reset function to increase the counter value by the reference clock. MSB of the counter 33 means its most significant bit. Further, there is provided a D-type flip-flop 34 to generate output clock by dividing output of the counter 33 into two. From the D-type flip-flop 34, output clock is output as window pulse.
In the conventional VFO thus composed, for example, when the transfer rate of data is 500 kbps and the frequency of reference clock is 12 MHz, the counter value is set to be six so that playback data comes to the center of the high width or low width of the output clock every time playback data is input, thereby the phase compensation is conducted quickly. Meanwhile, the ideal cycle of the counter 33 to generate the output clock is 12 in the decimal system.
FIG. 2 is a timing chart showing an example of erroneous correction to a pair of peak shifts. In FIG. 2, solid lines indicate the output clock that is corrected erroneously, and dotted lines indicate the output clock in a case that the correction of output is not conducted. Here, data to be played back is “11”, and shown is a case that both of the bits are subject to peak shift where they shift off to the right or left side from the center. Essentially, when playback data arises, the output clock has to be output at a high timing referenced to the output clock. But, as shown in FIG. 2, in the conventional VFO, when the peak shift occurs in playback data, the timing of output clock at the arising of playback.